A technology that's seen periodic improvements over the years, Enhanced Intel SpeedStep technology has been included in almost every single processor since the original Intel SpeedStep technology debuted in early 2001. Find out exactly what it does below. You'll also find a complete processor support list for this technology on this page.

Enhanced Intel SpeedStep technology (EIST) is a power-saving feature first introduced with Intel's Pentium III-M processors, codenamed Tualatin, back in July 2001. It's essentially a newer and more refined version of the older Intel SpeedStep technology, first introduced with Mobile Pentium III processors, codenamed Coppermine, in January 2001.

Over the years, it has seen numerous improvements, each time getting more and more power efficient. It's still in use today by all modern Intel processors under the Celeron, Pentium, Core M, Core i3, Core i5, Core i7 and Xeon family names.

The latest revision, 3.2, is adapted for multi-core processors and hasn't changed since its introduction in January 2006 with the Core Duo and Core Solo processors, also known by their codename, Yonah. To take advantage of this technology, your laptop must be using a processor that supports the feature, in conjunction with a compatible chipset and the laptop's BIOS must also support the feature and have it enabled.

When the processor isn't required to perform at its maximum capacity, it can use this technology to reach slower frequencies, allowing it to reduce the amount of power it consumes, and therefore also reducing the amount of heat it outputs.

The technology was created to allow processors to slow themselves down and even turn off parts of their cores to help save power and also heat output. The technology is most commonly found in laptop and embedded processors, where power-saving is typically considered over absolute performance, and in turn provides better battery life. However, modern Intel desktop processors, including the Core2 Duo range, are also equipped with the technology.

EIST works by simultaneously halving the front-side bus base clock frequency, and lowering the clock multiplier. The achieved core frequency is the absolute lowest operating mode, while the processor is still in use.